VLSI & ASIC Digital design interview questions
Digital design interview questions & answers.
21) Design a four-input NAND gate using only two-input NAND gates ?
A:Basically, you can tie the inputs of a NAND gate together to get an inverter, so...
22)Difference between Synchronous and Asynchronous reset.?
Synchronous reset logic will synthesize to smaller flip-flops, particularly if the reset is
gated with the logic generating the d-input.
But in such a case, the combinational logic gate count
grows, so the overall gate count savings may not be that significant.
The clock works as a filter for small reset glitches; however, if these glitches occur near
the active clock edge, the Flip-flop could go metastable.
In some designs, the reset must be generated by a set of internal conditions. A
synchronous reset is recommended for these types of designs because it will filter the
logic equation glitches between clock.
Disadvantages of synchronous reset:
Problem with synchronous resets is that the synthesis tool cannot easily distinguish the
reset signal from any other data signal.
Synchronous resets may need a pulse stretcher to guarantee a reset pulse width wide
enough to ensure reset is present during an active edge of the clock[
if you have a gated clock to save power, the clock may be disabled coincident with the
assertion of reset. Only an asynchronous reset will work in this situation, as the reset
might be removed prior to the resumption of the clock.
Designs that are pushing the limit for data path timing, can not afford to have added gates
and additional net delays in the data path due to logic inserted to handle synchronous
resets.
Asynchronous reset :
The biggest problem with asynchronous resets is the reset release, also called
reset removal.
Using an asynchronous
reset, the designer is guaranteed not to have the reset added to the data path.
Another advantage favoring asynchronous resets is that the circuit can be reset with or
without a clock present.
Disadvantages of asynchronous reset:
ensure that the release of the reset can occur within one clock period.
if the release of the reset occurred on or near a clock edge such
that the flip-flops went metastable.
23) Why are most interrupts active low?
This answers why most signals are active low
If you consider the transistor level of a module, active low means the capacitor
in the output terminal gets charged or discharged based on low to high and
high to low transition respectively. when it goes from high to low it depends on
the pull down resistor that pulls it down and it is relatively easy for the output
capacitance to discharge rather than charging. hence people prefer using
active low signals.
24)Give two ways of converting a two input NAND gate to an inverter?
(a) short the 2 inputs of the nand gate and apply the single input to it.
(b) Connect the output to one of the input and the other to the input signal.
25) What are set up time & hold time constraints? What do they signify? Which one is
critical for estimating maximum clock frequency of a circuit?
set up time: - the amount of time the data should be stable before the application of
the clock signal, where as the hold time is the amount of time the data should be stable
after the application of the clock. Setup time signifies maximum delay constraints; hold
time is for minimum delay constraints. Setup time is critical for establishing the
maximum clock frequency.
26) Differences between D-Latch and D flip-flop?
D-latch is level sensitive where as flip-flop is edge sensitive. Flip-flops are
made up of latches.
27) What is a multiplexer?
Is a combinational circuit that selects binary information from one of many
input lines and directs it to a single output line. (2n =>n).
28)How can you convert an SR Flip-flop to a JK Flip-flop?
By giving the feed back we can convert, i.e !Q=>S and Q=>R.Hence the S and
R inputs will act as J and K respectively.
29)How can you convert the JK Flip-flop to a D Flip-flop?
By connecting the J input to the K through the inverter.
30)What is Race-around problem?How can you rectify it?
The clock pulse that remains in the 1 state while both J and K are equal to 1 will
cause the output to complement again and repeat complementing until the pulse goes
back to 0, this is called the race around problem.To avoid this undesirable operation,
the clock pulse must have a time duration that is shorter than the propagation delay
time of the F-F, this is restrictive so the alternative is master-slave or edge-triggered
construction.
31)How do you detect if two 8-bit signals are same?
XOR each bits of A with B (for e.g. A[0] xor B[0] ) and so on.the o/p of 8 xor gates
are then given as i/p to an 8-i/p nor gate. if o/p is 1 then A=B.
32)7 bit ring counter's initial state is 0100010. After how many clock cycles will it return
to the initial state?
6 cycles
33) Convert D-FF into divide by 2. (not latch)
What is the max clock frequency the circuit can handle, given the
following information?
T_setup= 6nS
T_hold = 2nS
T_propagation = 10nS
Circuit:
Connect Qbar to D and apply the clk at clk of DFF and take the O/P at
Q. It gives freq/2.
Max. Freq of operation:
1/ (propagation delay+setup time) = 1/16ns = 62.5 MHz
34)Guys this is the basic question asked most frequently. Design all the
basic gates(NOT,AND,OR,NAND,NOR,XOR,XNOR) using 2:1
Multiplexer?
Using 2:1 Mux, (2 inputs, 1 output and a select line)
(a) NOT
Give the input at the select line and connect I0 to 1 & I1 to 0. So if A
is 1, we will get I1 that is 0 at the O/P.
(b) AND
Give input A at the select line and 0 to I0 and B to I1. O/p is A & B
(c) OR
Give input A at the select line and 1 to I1 and B to I0. O/p will be A | B
(d) NAND
AND + NOT implementations together
(e) NOR
OR + NOT implementations together
(f) XOR
A at the select line B at I0 and ~B at I1. ~B can be obtained from (a)
(g) XNOR
A at the select line B at I1 and ~B at I0
35)N number of XNOR gates are connected in series such that the N
inputs (A0,A1,A2......) are given in the following way:
A0 & A1 to first XNOR gate and A2 & O/P of First XNOR to second XNOR gate
and so on..... Nth XNOR gates output is final output. How does this
circuit work? Explain in detail?
If N=Odd, the circuit acts as even parity detector, ie the output will
1 if there are even number of 1's in the N input...This could also be
called as odd parity generator since with this additional 1 as output
the total number of 1's will be ODD.
If N=Even, just the opposite, it will be Odd parity detector or Even
Parity Generator.
36)An assembly line has 3 fail safe sensors and one emergency shutdown
switch.The line should keep moving unless any of the following conditions
arise:
(i) If the emergency switch is pressed
(ii) If the senor1 and sensor2 are activated at the same time.
(iii) If sensor 2 and sensor3 are activated at the same time.
(iv) If all the sensors are activated at the same time
Suppose a combinational circuit for above case is to be implemented
only with NAND Gates. How many minimum number of 2 input NAND
gates are required?
No of 2-input NAND Gates required = 6
You can try the whole implementation.
37)Design a circuit that calculates the square of a number? It should not
use any multiplier circuits. It should use Multiplexers and other logic?
This is interesting....
1^2=0+1=1
2^2=1+3=4
3^2=4+5=9
4^2=9+7=16
5^2=16+9=25
and so on
See a pattern yet?To get the next square, all you have to do is add the
next odd number to the previous square that you found.See how
1,3,5,7 and finally 9 are added.Wouldn't this be a possible solution to
your question since it only will use a counter,multiplexer and a couple
of adders?It seems it would take n clock cycles to calculate square of
n.
38) How will you implement a Full subtractor from a Full adder?
all the bits of subtrahend should be connected to the xor gate. Other
input to the xor being one.The input carry bit to the full adder should be made 1.
Then the full adder works like a full subtractor
39)A very good interview question...
What is difference between setup and hold time. The interviewer was
looking for one specific reason , and its really a good answer too..The
hint is hold time doesn't depend on clock, why is it so...?
Setup violations are related to two edges of clock, i mean you can vary
the clock frequency to correct setup violation. But for hold time, you
are only concerned with one edge and does not basically depend on
clock frequency.
40)In a 3-bit Johnson's counter what are the unused states?
2(power n)-2n is the one used to find the unused states in johnson
counter.
So for a 3-bit counter it is 8-6=2.Unused states=2.
the two unused states are 010 and 101
