## Digital interview questions Page 1 Page 2 Page 3 Page 4 Page 5

*(a)
**2 ^{48 }*≈

a. ABC + ABC’ + A’B

b. (A + B)’(A’ + B’)

c. (A + B’ + AB’)(AB + A’C + BC)

d. ((A + B)C’+AB’)B’D

a. ABC + ABC’ + A’B = AB(C + C’) + A’B (T8)

= AB + A’B (T5)(T1’) = B(A + A’) (T6’)(T8) = B (T5)(T1’)

b. (A + B)’(A’ + B’)

= A’B’(A’ + B’) (T13) = A’B’ + A’B’ (T8)(T6’)(T3’) = A’B’ (T3)

c. (A + B’ + AB’)(AB + A’C + BC)

= (A + AB’ + B’ + AB’)(AB + A’C) (T3)(T6)(T11) = (A + B’)(AB + A’C) (T9) = AB + A’B’C (T8)(T5’)(T2’)

d. ((A + B)C’+AB’)B’D

= (B’A + BC’ + AC’)B’D (T6’)(T8)(T6) = (B’A + BC’)B’D (T11) = AB’D (T6’)(T5’)(T2’)

This circuit is F=A’B’+AB+AC = (A+B’)(A’+B+C). After entering both circuits, the output is, indeed, zero everywhere. The XOR gate is zero when the inputs are equal and since these circuits are equivalent, the output is always zero.

From the diagram we find that F=AD’+A’C’+A’C’D’+A’B’C. First, let’s see what the minimal equations are in both SOP and POS forms:

For each parallel inverter driving the same load, the speedup is about 2x. For A we have a delay of 2 units. In B, we have 0.5 units for the first group and 1 unit for the second group for a total of 1.5 units. For C, we have 1 unit for the first group for the load is twice as much to drive two inverters as one; the second group has 0.5 unit delay and the last inverter has 1 units for a total of 2.5 units. Circuit D is the best with the first group of inverters having 0.5 units delay and the second group having 0.5 units delay for a total of 1 unit delay.<br><br> Circuit D is the fastest, and circuit C is the slowest!

The circuit has five 2-input NAND gates and one 3-input NAND gate. Each 2-input NAND gate takes four transistors and each 3-input NAND gates needs six. So (5*4) + 6 = 26 transistors

X = (A + DF’)(BC + BC’E)

Y = (B’+C’E’) + (A’D + AD’ + DF)

Z = AB(C + E)(D’ + A’F)

If we are a little clever and let

Y =(U + (A’D + AD’ + DF)

Z = AU(D’ + A’F) [ for BC+BC’E = B(C+E)]

First, see if A<B. If it is, we will get a negative number that equals –(B-A). If A>B then we get a positive number that is A-B. Directly implementing this is what the diagram does.

Assume that each flip-flop has a setup time of 2 ns, a hold time of 3 ns and a clock-to-output delay of 5 ns. Further assume that each gate has a delay of 2 ns except each inverter has a delay of 1 ns. What is the maximum clock frequency that you can clock the following circuits. Also discuss what constraints are placed on the inputs. ?

a. From clock, we wait 5 ns for Q to change so we meet the hold time (3 ns) with no problems. Setup time is 2 ns and we need to wait at least 6 ns (5+1 ns) for the output to show up at the input, D. Hence, we can clock this every 6+2 ns = 8 ns or 125 MHz.

b. Again, hold is not a problem but the delay is now 7 ns from clock to the Q output showing up at D. Adding setup, 7+2 = 9 ns, we can clock at about 111 MHz. Input

c. Here, the worst case delay is from the clock to the output of the first flip-flop (5 ns), through the AND gate (2 ns) and to the D input (2 ns setup). There is no hold time problem with this circuit since all delays are more than 3 ns. Input

First, let’s look at hold time: Hold time violations occur when we clock a flip-flop and this
causes the output to propagate to a flip-flop input before the hold time is
satisfied. Hence, look for the shortest path from Q to D. This occurs from Q_{B
to D}B and D_{B. With a clock skew of 1 ns, however, the worst case is
when that causes Q}B to change before flip-flop A ever gets clocked!
(There can be no clock skew when the output goes to the input of the same
flip-flop.) Hence, the worst case hold time is from QB to DA through
the one OR gate. The total delay could be as fast as 1 ns flip flop propagation
delay + 0.5 ns OR gate delay = 1.5 ns while we might need to hold the value for
1 ns clock skew + 1 ns hold time = 2 ns. Hence, we have a problem and to fix it
we will add two inverters (0.5 ns delay on both) to the feedback of QB to
lengthen this path to 2.5 ns which is greater than the hold time we need (2
ns). All other feedback paths are at least 2 ns so we are OK on them. Now, the
setup time analysis will tell us how fast we can clock the circuit. We see that
the longest path from Q to D is from Q_{A }to D_{A}. Since this
is from the Q to D of the same flip-flop, let’s also look at the longest path
between the flip-flops to be sure clock skew doesn’t affect this analysis.

From Qto DA_{A A}: 3
ns flip flop propagation delay + 3*2 ns comb. circuit delay + 2 ns setup time =
11 ns. From Q_{B} to D: 3 ns flip flop propagation delay + 3*2 ns comb. circuit
delay (don’t forget our added inverters!) + 1 ns clock skew + 2 ns setup time =
12 ns. Using the maximum values for the propagation delays we found that the
period must be at least 3+(3*2)+1+2=12 ns. If the clock changes at t=0, then X
must be stable starting at t=-6 and continuing until t=0. If the clock can
change anytime within 1 ns of t=0, then X must be stable starting a t= -7 and
continuing until time t =+1. The output Z can change anytime between t= +1.5 ns
and t= +5ns, if the clock changes at t=0, but if the clock can change anytime
in the interval between –1 and +1, then the output can change anytime between
+.5 and +6.

The following circuit is used as a synchronizer for the traffic sensor used on the traffic controller designed in class. Assume the traffic controller is clocked with a 10 Hz clock. We expect the sensor to be activated about once a minute during the day.

How fast should we clock this synchronizer? Since it is a synchronizer, we must clock it at the same speed as the state machine we’re feeding: 10 Hz. Any other clock rate and we’re not synchronized!

b. Shouldn’t we have a reset on these flip-flops? Why or why not?

If we do not reset both flip-flops and either flip-flop starts at a logic 1 when the SENSOR_IN is not, then we might get a false-positive on the sensor in put and make the light change when no cars are around. This is only a problem at startup of the system, however. After this initial startup period, the SENSOR_IN will be a logic 0 and will, effectively, reset this synchronizer for us. If we don’t care what happens when we turn the system on, we can ignore reset, but we probably should have a reset to be robust. The only problem is then we must ensure that the reset timing is such that we don’t have a possible metastability issue.

c. Assuming we clock this synchronizer at 10 Hz, can we assume that since the input, SENSOR_IN, only changes once a minute (1/60 Hz) that it will never fail (i.e. latch a metastable state)? No. The probability is low, but nothing is guaranteed! If we happen to have a car arrive on the sensor just as this circuit is getting clocked, we will violate a setup and/or hold time and have the possibility of a metastable state being latched.

d. Assuming we cannot change the clock frequency or rate of input changes, is there any way to reduce the probability that we will have a failure of the synchronizer? If we have flip-flops with shorter setup times this will give us a smaller chance of violating it and will also give us a longer resolution time. Other than that, there is nothing we can do.