JTAG TAP Controller
JTAG project properties
Category :: JTAG controller
Language :: Verilog
Development status :: Production/Stable
This implementation of the Test Access Port (TAP) is fully IEEE 1149.1 compliant. It includes a TAP controller, a 4-bit instruction register and three test data registers: idcode register, bypass register and boundary scan register. Boundary scan register is connected to eight pins (2 inputs, 2 outputs, 2 tristatable outputs and 2 bidirectional pins). Besides the Verilog code, a BSDL file is also provided. The number of pins can be easily increased by following the instructions. The design had been tested with the JTAG Technologies testing equipment (The TAP controller was implemented in Xilinx 95144XL). The design will be expanded in the future to support additional instruction and debug capabilities.