VLSI Interview Helpful Resources Main Page

This page contains some very useful VLSI Documentation & tips that is must read before VLSI interview

Some of the common questions asked in vlsi interview are related to topics such as Timing analysis , Synthesis Constraints,
VlSI design flow, FSM's, Clocking Strategies, Bulit in self test BIST, BoundarScan, Design for Testability, Fault Simulation ,
Setup & Hold Time & RTL Coding Guidelines are presented in detail in this page.

These VLSI documents can be used for general reading as well.

RTL Coding Guidelines

Timing Tutorial

RTL Coding Guidelines

Synthesis ppt tutorial

VLSI Design Flow

Verilog case.pdf

Writing FSM in Verilog

Synopsis Constraints

Clocking Strategies

Bulit in self test BIST

Very good document on ASIC_Design

BoundarScan BS

Design for Testability DFT

Fault Simulation

Full list of Xilinx & CPLD with all features

Setup,Hold Time

Analog IC Design Process

Accellera SystemVerilog Workshop

Verilog Event-Driven Simulation

Important Commands in VLSI

Cadence Commands